Date
Fraunhofer IZM wrote:
#Project #News
The work of the PUNCH Project demonstrates how #advanced #packaging can bring #photonics and #electronics closer together, paving the way for next-generation AI and high-performance computing interconnects.
PUNCH will demonstrate a 1.6 Tb/s co-packaged optical transceiver that co-integrates a photonic IC (PIC) with eight high-speed electronic ICs (EIC) inside a compact fan-out wafer-level package (FOWLP). By combining high-density electrical redistribution layers with scalable optical interconnect technologies, both electrical and optical integration is combined.
𝐇𝐢𝐠𝐡𝐥𝐢𝐠𝐡𝐭𝐬:
✅ 32-channel optical transceiver (4 spatial channels × 8 wavelengths)
✅ PIC + 8 driver/TIA EICs integrated in a single FOWLP (see photo)
✅ Integration of the FOWLP with high-end IC substrates (ongoing)
✅ Optical access through either direct fiber-array attachment or a polymer optical redistribution layer (ORDL)
✅ Underlying technologies allow for scaling to 3.2 Tb/s and 6.4 Tb/s
This is a collaborative effort from imec / Ghent University (coordination, IC design, optical transceiver design and testing, ORDL technology), Fraunhofer IZM (FOWLP technology), AT&S (IC substrate integration) and PHIX Photonics Assembly (Optical packaging).
#CoPackagedOptics #SiliconPhotonics #AdvancedPackaging #FOWLP #OpticalInterconnects #DataCenter #AIInfrastructure
Picture: Co-packaged optical transceiver. Copyright: Fraunhofer IZM
Leonie Leadbetter , Robert Gernhardt , Jeroen Missinne , Geert Van Steenberge and much more
The work of the PUNCH Project demonstrates how #advanced #packaging can bring #photonics and #electronics closer together, paving the way for next-generation AI and high-performance computing interconnects.
PUNCH will demonstrate a 1.6 Tb/s co-packaged optical transceiver that co-integrates a photonic IC (PIC) with eight high-speed electronic ICs (EIC) inside a compact fan-out wafer-level package (FOWLP). By combining high-density electrical redistribution layers with scalable optical interconnect technologies, both electrical and optical integration is combined.
𝐇𝐢𝐠𝐡𝐥𝐢𝐠𝐡𝐭𝐬:
✅ 32-channel optical transceiver (4 spatial channels × 8 wavelengths)
✅ PIC + 8 driver/TIA EICs integrated in a single FOWLP (see photo)
✅ Integration of the FOWLP with high-end IC substrates (ongoing)
✅ Optical access through either direct fiber-array attachment or a polymer optical redistribution layer (ORDL)
✅ Underlying technologies allow for scaling to 3.2 Tb/s and 6.4 Tb/s
This is a collaborative effort from imec / Ghent University (coordination, IC design, optical transceiver design and testing, ORDL technology), Fraunhofer IZM (FOWLP technology), AT&S (IC substrate integration) and PHIX Photonics Assembly (Optical packaging).
#CoPackagedOptics #SiliconPhotonics #AdvancedPackaging #FOWLP #OpticalInterconnects #DataCenter #AIInfrastructure
Picture: Co-packaged optical transceiver. Copyright: Fraunhofer IZM
Leonie Leadbetter , Robert Gernhardt , Jeroen Missinne , Geert Van Steenberge and much more
