Smart power ASIC design

The CMST research team has acquired experience in the field of the full-custom design of Application Specific Integrated Circuits (ASICs). These chips usually contain mixed analogue-digital functions, and are designed in a wide variety of technologies, ranging from standard BIMOS and CMOS to the most advanced technologies such as I²T (Intelligent Interface Technology), which allows us to integrate high-voltage devices (up to 100V) in a sub-micron CMOS process.

Our researchers are involved in al phases of the design process of these integrated circuits:

• conception and design of the electronic schematics
• extensive simulations of the electrical behaviour
• drawing of the complete chip layout.

For the manufacturing of the designed ASICs, the team normally relies on the AMI Semiconductor foundry at Oudenaarde, Belgium, while the testing and characterisation of the produced chips is performed within our group..

Regarding the applications, the research team focuses mainly on 2 different fields:

• driver circuits for various types of flat-panel displays
• driver chips for opto-electronic components

Since a few years, the CMST research team is also active in the field of two-dimensional TCAD simulations on high-voltage transistors in I²T and other sub-micron CMOS technologies (1,2). 

Driver circuits for flat-panel displays

An example of this application field is a recently developed integrated driver circuit for a special kind of LCD that requires very complex signals and high voltage levels. This ASIC was designed in the I²T technology and is capable of synthesising the required complex waveforms with the necessary amplitudes (up to 100V_pp), starting from a 3V battery power supply (Figure 1). During the design of the electronic schematics of this chip, the team invented a completely new architecture, allowing us to reduce the internal power consumption of the chip to an absolute minimum. This was of utmost importance for the envisaged application: a camera watch (see picture below)

"Iris" camera watch

The LCD driver chip shown above was developed during the Esprit project "Helicos" (1998-2001), following specifications outlined in close co-operation with partner Asulab.
Asulab is the Swatch Group corporate R&D lab, and develops innovative watch (sub)systems and manufacturing techniques.
In the Swatch Group's 2003 annual report, the "Iris" camera watch is presented (Figure 2), which contains a bi-stable display that is driven by the advanced ultra-low-power high-voltage driver chip. According to this report, the water-resistant watch comprises a high quality digital camera with an infrared link to a PC, and is operated using invisible "T-Touch" sensitive pads. It has sufficient memory for 31 high resolution color images, and thanks to the consequent low-power design, the primary battery allows for 500 pictures to be taken.

Mjollnir: a row driver chip for AFLC displays

During the IST project Hemind, a special driver chip was developed for the addressing of an antiferroelectric passive matrix liquid crystal display. The driver chip has 300 outputs, is bidirectional and cascadable. Each output is a 60V high-voltage analog multiplexer selecting one of 7 high-voltage levels (5-60V) or ground. This allows maximum flexibility in waveform generation. The chip works on a 3.3V supply but the 7 HV levels need to be generated externally. The chip is not only suited for driving AFLC displays but also for other applications where a complicated HV waveform needs to be applied to a great number of lines consecutively.

> Mjollnir datasheet (pdf)

Driver chips for opto-electronic components

A nice example of the second application field is the 0.7m m CMOS transconductance amplifier from Figure 4, being part of an active probe for measuring the electric component of weak electromagnetic fields (3). The task of this ASIC is to amplify the weak voltage fluctuations, captured by a miniature dipole antenna, and to transform them into current variations through a laser diode. The major challenge in this design was to combine a relatively high output current level (10 to 20mA), required for optimum laser operation of the diode, and a high bandwidth (at least 500MHz).

Figure 4: A high-bandwidth transconductance amplifier made in a 0.7 µm CMOS technology.

TCAD

TCAD (Technology Computer Aided Design) simulates numerically physical phenomena occurring during the making of semiconductor devices and their electrothermal behaviour onto a non-uniform grid or mesh in 1, 2, or 3 space dimensions with time dependency when necessary. Physical models are used to simulate a complete fabrication sequence, process step by process step. As such, devices can be made starting from scratch (e.g. a silicon wafer). The final result is a real semiconductor device (e.g. a transistor), represented in the so-called process simulator as a 'virtual' structure whose physical properties are discretized onto a mesh of nodes and can be viewed using graphical interfaces. The operation of the 'virtual' structure is then simulated by solving numerically the fundamental semiconductor transport equations and the Maxwell equations. The graphical interfaces make it possible to see what is happening in a device under whatever operation condition thinkable. This important asset is used many times in literature to discuss, understand and analyze problems of all kind.

In CMST, TCAD is used to develop power devices as an extension to standard CMOS. A calibrated CMOS process flow (e.g. 0.35 mm) of our industrial partner (AMI Semiconductor) serves as a basis to which process layers are added in order to cope with the high voltage and power requirements. This virtual wafer fab (that is, the TCAD software) is used to design and develop power devices, to think up new concepts, and to anticipate problems. The result of the TCAD work is then used as an input for the silicon foundry. The final goal is to create a smart power technology integrating complex digital functions and power management on a single chip.

In the past, a 0.7 µm smart power technology (AMIS' I2T technology) has been developed successfully using TCAD. CMST has contributed to this process within the frame of several projects, either funded by the European community (AUTOMACS) or the Flemish government. In the last few years TCAD at CMST focuses on a 0.35 µm smart power technology (AMIS' I3T technology). After calibration of the standard CMOS process flow and the development of various DMOS devices (of which the pDEMOS was developed at CMST) in the DMOS project funded by the Flemish Government; a new project (COMPOSE) has been started which purpose is to integrate new devices and/or device concepts in the I3T technology. This far, a lateral IGBT (Insulated Gate Bipolar Transistor) was designed in the junction isolated I3T technology (Figure 5). With the help of extensive TCAD simulations, an LIGBT was created that no longer suffers from substrate current generation (Figure 6). At the same time, a European funded project called ROBUSPIC is running, of which the main objective is to build compact models that accurately describe power device operation. TCAD simulations done at CMST are used by European partners (EPFL) to help with the understanding of the DMOS devices and thus with the compact modelling.

Figure 5: Lateral IGBT in a junction isolated technology at on-state breakdown. The black lines show the hole current at that stage.